Sunsys launches the industry's first ultra-Ethernet and UALink IP solution to connect large-scale AI accelerator clusters

Synopsys, Inc announced the introduction of the industry's first ultra-Ethernet IP and UALink IP solutions, including controllers, PHYs, and validation IP, to address the demand for standards-based, high-bandwidth, and low-latency HPC and AI accelerator interconnects. Hyperscale data center infrastructure is accelerating and must scale to hundreds of thousands of accelerators with efficient and fast connections to support the processing of trillions of parameters in large language models. Syrus Ultra Ethernet and UALink IP will provide a holistic, low-risk solution for high-speed, low-latency communications to scale and extend the AI infrastructure architecture.

Neeraj Paliwal, senior vice president of IP Product Management at Syrs, said: "For more than 25 years, Syrs has been at the forefront of providing the world's leading IP solutions that enable developers to accelerate integration based on standard features. Based on the industry's first hyper-Ethernet and UALink IP, our partners can spearhead the development of a new generation of high-performance chips and systems with broad interoperability to expand future-proof AI and HPC infrastructure."

Syrs Ultra Ethernet IP solutions support scaling to millions of endpoints

The leading performance of the new Syrs Ultra Ethernet IP solution includes: IP solutions for Scalable back-end networks: The Synos Ultra Ethernet IP solution, consisting of PHY, MAC and PCS controllers and validation IP, provides a low-risk path for developers to develop systems that can support up to one million endpoints in a single network.

The world's leading 224G Ethernet PHY IP: The silicon-proven Syns 224G Ethernet PHY IP supports HyperEthernet protocols and has demonstrated its extensive interoperability at several industry shows, including ECOC, OFC and DesignCon.

Patented error correction implementation: Syrs Ultra Ethernet MAC and PCS controller IP delivers bandwidth of up to 1.6 Tbps and ultra-low latency for real-time processing required by AI workloads.

Seamless integration: MAC and PCS IP support higher level interfaces with the hyper-Ethernet stack, providing a complete chip implementation for switches, AI accelerators, and smart nics.

Accelerate verification and validation: The Synovate Ultra Ethernet Verification IP helps ensure protocols meet rapidly evolving industry standards, enabling faster and more efficient validation of AI and HPC systems.

Debashis Basu, senior vice president of engineering at Juniper, said: "Based on our proprietary Express 5 ASIC technology and Syrs' Ethernet IP, Juniper has pioneered the PTX10002-36QDD Packet Transport Router, becoming the first in the industry to offer 800GbE capability. We will continue to work with Synopsys and leverage new technologies from the Ultra Ethernet Alliance (UEC) to evolve into the 1.6TbE era." It also means that we will continue to innovate in high-speed networks to achieve our goal of significantly increasing the scale, reliability and performance of data center networks. More importantly, as AI workloads continue to grow exponentially, it requires that these kinds of networks need to be more efficient and cost-effective."

Sunsys UALink IP solutions can significantly increase AI computing power The leading performance of the new Synovic UALink IP solution includes:

IP solutions that vertically scale compute structures: Syrs UALink IP solutions, consisting of a PHY, controller and validation IP, help developers accelerate development and support time-to-market systems with up to 1024 AI accelerators.

Efficient, high-speed data transfer: The low-power, high-bandwidth Syrs UALink PHY IP is designed for data-intensive AI workloads, delivering 200 Gbps per channel.

Latency optimization with memory sharing: The Synovate UALink controller IP helps alleviate critical bottlenecks in AI hardware infrastructure with shared memory access from accelerator to accelerator.

Built-in protocol check: The Syrs UALink verification IP is combined with Syrs Hardware Accelerated Verification solutions to provide fast and reliable verification of AI hardware.

Kurtis Bowman, Chairman of the Board of Directors of the UALink Consortium, said: "For decades, Syrs has consistently contributed to the creation of key interconnect standards in the industry through its leading technologies and has provided widely adopted high-speed interface IP. We are grateful to Synovs for their commitment to enabling UALink IP to create a scalable, high-performance data center ecosystem for developers to meet the growing demands of AI models."

Sunsys works with global industry leaders to connect AI accelerators at scale Robert Hormuth, vice president of architecture and strategy for AMD's Data Center Solutions group, said: "Advancing AI technology requires an industry-wide effort to build high-performance solutions that are critical to the future of the data center. The introduction of Sunsys' Ultra Ethernet and UALink IP with AMD's high-performance processors demonstrates our mutual commitment to creating an open, robust and scalable ecosystem for large-scale AI and high-performance computing."

Chris Petersen, Technology and ecosystem researcher at Astera Labs, said: "Advances in AI technology rely on industry collaboration to deliver scalable and energy-efficient high-performance accelerator structures. New interconnect technologies such as UALink will help support the rapid growth and complexity of AI and HPC workloads. We congratulate Sunsys for providing a new IP solution to support this critical connectivity ecosystem." David Bennett, Chief Customer Officer at Tenstorrent, said: "Being involved in defining and developing communications for AI systems based on open standards is a top priority for Tenstorrent. The low latency and high bandwidth of the upcoming UEC and UALink standards will enable ultra-efficient interfaces that support AI calculations with trillions of parameter models. Tenstorrent's RISC-V chips and Synovate's new UALink and Hyper-Ethernet IP will work together to support a super-large AI accelerator cluster."

Gerry Fan, CEO of XConn, said: "To keep up with the exponential growth in AI model parameters and computing demands, hyperscale enterprises need to address huge connectivity challenges. With XConn's UALink switches and Sunsys' new UALink IP, system architects can deploy high-performance, standards-compliant systems for the AI computing and networking architectures of the future."

Time to market and available resources Synopsys Hyper-Ethernet IP solutions, including MAC and PCS, PHY and verified IP, are scheduled to be available in the first half of 2025. The Syrus UALink IP solution, including controller, PHY and validation IP, is scheduled to be available in the second half of 2025.